1 August 2013
The continuing scaling of CMOS technology gives silicon ICs an increasingly high degree of integration. However, reliability issues are becoming more and more severe. Among the failure models observed in silicon ICs, electrostatic discharge (ESD) accounts for the highest proportion. Therefore it is necessary to carry out systematic and thorough analysis to reduce or even eliminate ESD issues, to improve the reliability of silicon ICs. With the advanced process nodes nowadays, the conventional silicon-based ESD protection devices are not meeting the demands of small size and high robustness. So, new materials-based devices, such as graphene transistors, are being investigated with the aim to develop high-performance devices. However, the reliability of graphene transistors under ESD stress also needs to be evaluated and their high-performance ESD protection should be investigated. So, we focus on the reliability of graphene transistors under ESD stress. We hope that our research could help the development of the application of graphene transistors.
In addition to conventional studies of graphene, such as how to produce high-quality and large-area graphene, how to select the single layer grapheme etc., we mainly investigate the electrical properties of graphene transistors. Graphene transistors, of which the conductive channel is graphene, are characterised with a similar method applied to MOSFET. We also investigate the DC characteristics of graphene transistors, such as drain to source currents under different gate voltages, and also the influence of different temperatures to the DC characteristics. Furthermore, we test graphene transistors under ESD stresses.
In our Letter, we present our investigation of the electrical properties of graphene transistors under DC measurement and ESD stresses. The response of graphene transistors to an ESD pulse, such as HBM (human body model) and very fast ESD Pulse, such as CDM (charged device model) is measured with transmission line pulsing (TLP) and very fast transmission line pulsing (VFTLP), respectively. The testing results show that there are no characteristics of snap back and the Graphene transistors show excellent robustness under different ESD stress. It shows that Graphene transistors could be excellent devices in integrated circuits, even without an additional ESD protection circuit. Furthermore, we can also design ESD protection for conventional silicon ICs based on Graphene transistors.
Graphene transistors have been regarded as a novel way to satisfy the high performance demands of the advanced process nodes. In future semiconductor processes, graphene may be deposited just as the common materials such as polysilicon or metals are today to form graphene transistors. Silicon ICs combined with graphene transistors can not only improve circuit performance, but could also improve the ESD protection level.
In the next step of this research, different electrode materials for the graphene transistors will be used to investigate the influence of electrical properties. The silicon-based ESD protection device design methods will be applied to the graphene transistors. Decisions about parameters, such as the length of the channel, will be made to optimise the possibility of ESD performance. The novel ESD protection devices based on graphene transistors could have an excellent performance with narrow window ESD, high robustness and low parasitic parameters.
There are various effects that need to be overcome with graphene transistors so that they can be integrated with today's silicon process. Graphene transistors cannot be completely turned off no matter how the gate is biased. The source-drain leakage current of graphene transistors will be the limiting factor when used in highly integrated, low-power circuits. And the substrate is also a key to influence on its band gap. At the moment it would seem that this problem could be solved with boron nitride.
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