20 June 2013
In 2005, around the time I started my PhD research at Stanford University, III-V semiconductors were starting to be reconsidered and re-evaluated. Intel announced that they were seriously considering placing digital III-V semiconductors in its future roadmap and Freescale reported the first successful dielectric stack on an In0.3Ga0.7As channel. However, in spite of all the research attention gained, no one had a clear picture of how III-V devices would perform against conventional technology even under ideal conditions. This intrigued me to start research on III-V semiconductors for digital logic applications.
During my graduate years, thorough investigation of performance limits of various III-V materials, elaborate simulation studies on band-structure and transport were reported. My research reflected a different perspective to raise and answer questions on key aspects of III-V semiconductors that were not immediately apparent at the time and yet vitally important, such as device footprint, parasitics, and PMOS operation as well as its impact on the circuit level.
Recent reports show III-V FETs scaled down to 30nm gate lengths and with high-κ dielectric gate insulator integrated onto a Si substrate. Having seen these promising experimental results on III-V logic ‘devices’, it is important to understand the issues related to ‘circuits’ in future VLSI technology generations. Therefore, I developed a physics-based III-V compact model that opens up the possibility for investigation of significant requirements such as electrostatics, series resistance, and many other design considerations for beyond-15nm technology generations.
An alternative solution for strained Si channel CMOS are high mobility channel materials such as III-V and Ge. In our Letter, we applied our physics-based compact model to project performance and power of circuits consisting of high mobility III-V/Ge transistors down to 11nm technology. Our studies show that high mobility channel materials with good carrier transport alone do not guarantee higher drive current at scaled lengths and reduced supply voltage. It quickly becomes apparent that loss of gate control and reduction in supply voltage reduces the gate overdrive needed for drive current capability. Only the most aggressive configuration with III-V-OI structure and optimistic scenario of series resistance met the ITRS target for drive current. We emphasise that realisation of good electrostatics, made possible by non-planar multi-gate structures, and low source/drain series resistance is crucial for the scalability of high mobility channel devices.
The semiconductor industry has faithfully followed Moore’s Law through tremendous research efforts and technological innovations. However, at shorter dimensions and lower power it becomes apparent that a switch to high mobility channel materials is inevitable. Industry is predicting the introduction of alternative channel materials such as Ge and III-V Indium-compounds around the 7nm node. In order to maintain electrostatic integrity for these devices, finFETs and gate all-around nanowire structures must be incorporated to achieve sharp turn-off. Over the next decade, it will be an exciting time where we will witness a mixture of innovations in material, structure, interconnects, and integration as well as a possible paradigm shift leading into new territories where quantum information of electrons such as spin is used for switching.
Device research effort in the III-V community is now focused on challenges such as the high-k dielectric to semiconductor interface quality, a viable PMOS candidate, and the heterogeneous integration on a silicon platform. Also maintaining low series resistance while dimensions thin down impose a significant challenge to future devices and circuits. Devices that operate under different switching mechanisms such as tunnel FETs and mechanical relays that overcome the 60mV/dec slope are possible solutions to low-power applications at ultra-scaled supply voltages.
Growing different materials for NFET and PFET on 450mm silicon wafers and patterning sub-10nm lengths at supply voltages as low as 0.5V in a 3D stacked architecture, all while being cost-effective, will be a tremendous challenge. This means research across a wide spectrum of areas will be important. An exciting future for nanoelectronics lies ahead of us.
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