25 April 2013
A US-based team have expanded their model of III-V materials interfaces to include series resistance and dielectric leakage behaviour.
With conventional planar CMOS topology reaching a scaling limit at the 20 nm node attention has shifted to 3D FinFET and Tri-gate structures. However, 3D MOSFETs will not be able to sustain a CMOS performance boost for long and researchers are exploring the options beyond them. III-V materials are important to these efforts because of the high carrier mobility they can provide.
III-V materials have a long history in transistors including HBTs and HEMTs but have not been the first choice for MOSFETs - the fundamental technology for modern large scale integrated circuits including the SoC devices used in everyday devices like smartphones.
A major impediment for III-V material MOSFETs is the quality of the dielectric and dielectric/semiconductor interface. For perspective, a key factor in the choice of silicon for CMOS technology was that its native oxide has good interface quality. So modelling and understanding the III-V material interface is critical and that means understanding the gate dielectric bulk-oxide trap. This is not a concern for silicon-based MOS capacitors with their native oxide interfacial layer, however, bulk-oxide traps are responsible for the large frequency dispersion of III-V MOS capacitors in the accumulation region.
The team from the University of California – San Diego and Stanford University previously produced the first bulk-oxide trap model for III-V materials to reflect the distributed nature of bulk-oxide trap capacitance over the depth of the gate dielectric. The model was successfully applied to many III-V MOS capacitor samples but focussed on the intrinsic effects of the bulk-oxide trap without considering parasitic components.
But parasitic components can be significant and in their latest work the team address the impact of two of the most important – series resistance and dielectric leakage. In this context series resistance is the parasitic resistance associated with the conducting path and dielectric leakage is the leakage current flow across the gate dielectric of a MOS capacitor.
In the work reported in their Letter the California-based team have added these parasitic components to the model and studied their impact on capacitance-voltage (C-V) and conductance-voltage (G-V) frequency dispersion in the accumulation region. Providing a simple method to extract the series resistance and dielectric leakage conductance values from measured capacitance and conductance data, the new model is able to explain and fit dispersion data that the previous model could not. Team member Professor Yuan Taur explained that “The uptick of conductance data at high frequency has often been observed in other III-V MOS works. This model provides a satisfactory explanation for the first time.”
The new model has shown that series resistance is not the cause of C-V frequency dispersion in III-V MOS as it has a negligible effect on the total measured capacitance, but it can have a significant effect on the total measured conductance. This effect is proportional to the square of frequency, whereas the conductance component induced by bulk-oxide trap is proportional to frequency, allowing the team to separate the term associated with series resistance. Team member Dr Bo Yu said “The simple extraction method is also based on a couple of valid assumptions, but the new model itself is an accurate one without assumptions. In extreme cases where the assumptions break, we expect to learn from the model the complicated effect of series resistance and dielectric leakage in the presence of bulk-oxide trap contribution.”
For the team the major challenge in the work was confirming that series resistance and dielectric leakage were the cause of the odd U-shape of the conductance frequency dispersion data rather than other factors. However, when they found that the extracted series resistance is bias independent and the extracted dielectric leakage conductance drops quickly with gate voltage, which are consistent with series resistance and dielectric leakage assumptions, respectively, it confirmed to them that series resistance and dielectric leakage are sound explanations.
Fitting their model to measured C-V and G-V frequency dispersion data allows the extraction of bulk-oxide trap density, a key parameter for describing the dielectric quality of III-V MOS devices. The model has already been adopted for this by many research groups and the feedback the team has received indicates that the model matches most measured data closely and extracts reasonable trap densities across many samples.
Since conducting the work reported in their Letter, they have combined their bulk-oxide trap model with a traditional interface trap model to reproduce C-V and G-V frequency dispersion in regions from accumulation to strong inversion. Their current aim is to make the combined model more versatile with a view to making a general tool for the electrical characterisation of dielectric and interface quality that can become the gold-standard in this area.
This article is based on the Letter: Effect and extraction of series resistance in Al2O3-InGaAs MOS with bulk-oxide trap (new window).
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