This title is available electronically through the IET Digital Library
Author: Pierre-Emmanuel Gaillardon (ed.)
Product Code: PBCS0390
Stock Status: In stock
This book discusses one possible solution to the key issue in electronics engineering – the approaching limits of CMOS scaling – by taking advantage of the tendency of Schottky contacts to form at channel interfaces in nanoscale devices. Rather than suppressing this phenomenon, a functionality-enhanced device exploits it to increase switching functionality. These devices are Multiple-Independent-Gate-Field-Effect-Transistors, and other related nanoscale devices, whose polarity is electrostatically controllable. The functionality enhancement of these devices increases computational performance (function) per unit area and leads to circuits with better density, performance and energy efficiency.
Providing thorough and systematic coverage of enhanced-functionality devices and their use in proof-of-concept circuits and architectures. The theory and materials science behind these devices are addressed in detail, and various experimental fabrication techniques are explored. In addition, the potential applications of functionality-enhanced devices are outlined with a specific emphasis on circuit design, design automation and benchmarking.
Pierre-Emmanuel Gaillardon is an assistant professor in the Electrical and Computer Engineering department and an adjunct assistant professor in the School of Computing at The University of Utah, Salt Lake City, USA where he leads the Laboratory for NanoIntegrated Systems (LNIS). Professor Gaillardon is recipient of the BSF 2017 Prof. Pazy Memorial Research Award, the 2018 NSF CAREER award in functionality-enhanced transistors and the 2018 IEEE CEDA Pederson Award.
A compelling read for academics, research scientists and electronics engineers engaged in research into advanced electronics, and particularly functionality-enhanced devices.
This information is provisional and will be updated prior to publication
Chapter 1: Germanium based polarity controllable transistors - Walter M. Weber, Jens Trommer, Andre Heinzig, Thomas Mikolajick
Chapter 2: Two-dimensional materials for functionality enhanced devices- Prashanth Gopalan, Berardi Sensale-Rodriguez
Chapter 3: WSe2 polarity-controllable devices- Giovanni V. Resta, Iuliana P. Radu, Giovanni De Micheli, Pierre-Emmanuel Gaillardon
Chapter 4: Carrier type control of MX2 type 2D materials for functionality enhanced transistors - Shu Nakaharai
Chapter 5: Three-Independent Gate FET’s Super Steep Subthreshold Slope - Jorge Romero Gonzalez, Pierre-Emmanuel Gaillardon
Chapter 6: Super Sensitive Terahertz Detectors- Mehdi Hasan, Ross Walker, Pierre-Emmanuel Gaillardon, Berardi Sensale-Rodriquez
Chapter 7: CNT and SiNWFED Modeling for Ambipolar Logic Circuit Design - Xuan Hu, Wesley H. Brigner, Joseph S. Friedman
Chapter 8: Physical design of polarity controllable transistors - Odysseas Zografos, Pierre-Emmanuel Gaillardon, Giovanni De Micheli
Chapter 9: BCB Benchmarking for Three-Independent-Gate Field Transistors - Jorge Romero Gonzalez, Pierre-Emmanuel Gaillardon
Chapter 10: Exploratory Logic Synthesis for Multiple Independent Gate FETs - Luca Amaru, Pierre-Emmanuel Gaillardon, Subhasish Mitra, Giovanni De Micheli
Chapter 11: Ultrafine grain FPGAs with Polarity controllable Transistors - Xifan Tang, Pierre-Emmanuel Gaillardon, Ian O’Connor, Giovanni De Micheli
Chapter 12: Tunnel FET-Based Security Primitive Design - Yu Bi, Pierre-Emmanuel Gaillardon, X. Sharon Hu, Michael Niemier, Yier Jin