Routing for moore

24 April 2012

Researchers from the National Changhua University of Education in Taiwan have proposed a built-in self-routing scheme for through-silicon vias (TSVs).  The scheme, to be applied in three-dimensional integrated circuits (3D IC), improves repair rate, performance and reduces area overheads.  As Moore’s law begins to reach its limits, 3D ICs are becoming increasingly important for industry, and efficient interconnections are essential for their development.

Stacking up

A three-dimensional integrated circuit is, in essence, an integrated circuit in which the passive and active components can be manufactured along any one of three dimensions into a single circuit. In industry, a 3D IC usually means an integrated circuit stacked by two or more planar chips that are vertically interconnected. A via is a method for interconnection, consisting of two metal wires along different layers in the chips, and TSVs specifically denote the connection between two stacked planar chips.  For efficient processing it is important that the functioning vias are used, and that the faulty vias are repaired, which can be achieved through self-routing.

The stacked nature of these 3D ICs means they naturally address the spatial scaling problem, but reduction in size is not their only advantage, just as it is not the only problem.  “A number of positive indices double approximately every 18 or fewer months in semiconductor industry, which may include memory size per chip, transistor count per chip”, explained Professor Huang, “and this is the well-known Moore’s law that the industry has tried to pursue by scaling down some major parameters including dimension, supply voltage, threshold voltage and power consumption in recent decades”.  Unfortunately, scaling down these parameters is limited by the physics of the systems in two dimensions. “Thus 3D integration has become the key solution for reviving the Moore's Law from scaling limits due to process, voltage and thermal variations, power dissipation and interconnection delay”, said Huang.

Repairing the cube

3D ICs can be manufactured in many different processes and forms, including system-in-a-package (SIP) and hybrid memory cube (HMC), which was considered by Huang (see top image). “In 2010 we proposed a hypercube-based address remapping architecture for memory repair”, said Huang, “and then we started to study the channel concentrator that is actually a self-router, usually implemented by a sorting network or a Benes network”. Interestingly, the group found that their channel concentrator could be used to select good TSVs for repairing 3D ICs, especially for HMCs.

The major contribution of the method is to provide an area-efficient and high-performance TSV selector for repairing the 3D IC.  In fact, Huang has developed two categories of built-in self-routers. The preliminary structure improves the sorting network as an interconnect concentrator that can select any preferred interconnects from all TSVs, even for the many-TSV-fault model. The area overhead is reduced because the priority switching network looks like a parallelogram that can take only several cells in the width. Furthermore, the single stage of switches per tier means that the impact on the chip’s performance is minimal.  However, Huang admits that there is still work to be done:  “the disadvantage is that the width of the parallelogram will be the upper limit of the faulty TSV count when the area overhead is critical”.

Testing and redundancy

Having established the method for HMC processes, the group are hoping to apply it to others, such as SIP.  This is natural, said Huang, as their scheme “can be applied to all fault-tolerant interconnections where fault probability is not negligible”. They will also be combining it with other techniques, such as memory built-in self-testing (BIST) and built-in redundancy analysis.

While the group are looking to apply their techniques more widely, even the narrower field of TSV test and repair needs considerable development.  This future work will include TSV BIST, 3D IC test flow, inter-chip communication, standardisation, design for reliability and electronic design. However, Huang feels confident that “the synthesis of built-in self-router for TSVs will become a standard phase in future 3D IC design”.

The Letter presenting the results on which this article is based can be found on the IET Digital Library.
For further reading, please visit http://testlab.ncue.edu.tw/tch/

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