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Topic Title: VHDL couter 3bit xlinx ISE 11.1
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Created On: 15 February 2010 01:00 AM
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15 February 2010 01:00 AM
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tonyarn

Posts: 33
Joined: 26 January 2008

Hello

I am trying to make a counter 3bit in VHDL

some on can help me please ?

I have such this code

process (C, CLR)
begin
if (CLR='1') then
tmp = "0000";
elsif (C'event and C='1') then
tmp = tmp + 1;
end if;
end process;
Q = tmp;
end archi;

But I really do not understand how can i create a variable "tmp", also what means "event"

Tk so much

cheers

Antonio
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01 March 2010 07:36 AM
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tribull

Posts: 6
Joined: 28 November 2002

Hi Antonio,

"elsif (C'event and C='1') then"

event is a VHDL reserved word and in this instance is describing the rising edge of a clock. i.e has been an 'event' on C and it is also now equal to '1'.

Personally, these days I use

elsif rising_edge(C) then to describe the clock.






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