Decrease font size
Increase font size
Topic Title: VHDL couter 3bit xlinx ISE 11.1
Topic Summary:
Created On: 15 February 2010 01:00 AM
Status: Read Only
Linear : Threading : Single : Branch
Search Topic Search Topic
Topic Tools Topic Tools
View similar topics View similar topics
View topic in raw text format. Print this topic.
 15 February 2010 01:00 AM
User is offline View Users Profile Print this message


Posts: 33
Joined: 26 January 2008


I am trying to make a counter 3bit in VHDL

some on can help me please ?

I have such this code

process (C, CLR)
if (CLR='1') then
tmp = "0000";
elsif (C'event and C='1') then
tmp = tmp + 1;
end if;
end process;
Q = tmp;
end archi;

But I really do not understand how can i create a variable "tmp", also what means "event"

Tk so much


 01 March 2010 07:36 AM
User is offline View Users Profile Print this message


Posts: 6
Joined: 28 November 2002

Hi Antonio,

"elsif (C'event and C='1') then"

event is a VHDL reserved word and in this instance is describing the rising edge of a clock. i.e has been an 'event' on C and it is also now equal to '1'.

Personally, these days I use

elsif rising_edge(C) then to describe the clock.


See Also:

FuseTalk Standard Edition v3.2 - © 1999-2016 FuseTalk Inc. All rights reserved.