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Seminar on Heterogeneous Integration

Seminar

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Heterogeneous integration use packaging technology to integrate the dissimilar chips with different functions into a system or subsystem instead of integrating all the functions into a single chip and go for finer feature size.

Date and Time

03 October 2017 - 15:00-16:30

Location

Clear Water Bay, Hong Kong - icon_popup  (See map)

Organiser

Organised by the E & S.E Asia:Hong Kong local network.


About this event

Because of the drive of Moore’s law and compounded with the demands of mobile products such as smartphones and tablets, SoC (system-on-chip) has been very popular in the past 10+ years. SoC integrates ICs with different functions into a single chip for the system or subsystem. Unfortunately, the end of Moore’s law is fast approaching and it is more and more difficult and costly to reduce the feature size (to do the scaling) to make the SoC. Heterogeneous integration is against SoC. It has been a very “fancy” name in semiconductor packaging in the past few years. Heterogeneous integration use packaging technology to integrate the dissimilar chips with different functions into a system or subsystem instead of integrating all the functions into a single chip and go for finer feature size. For the next five years, we will see more of a higher level of heterogeneous integration, whether it is for performance, form factor, power consumption or cost. SiP (system-in-package) is similar to heterogeneous integration but with less density and gross pitch. In this lecture, the following topics will be presented. Emphasis is placed on the latest developments of these areas in the past three years. Their future trends will also be recommended.


 SoC
?Apple’s application process (A9)
?Apple’s application process (A10) 
SiP
?Amkor’s SiP for automobiles
?Apple Watch II (S2) assembled by ASE
Heterogeneous Integration with TSV-Interposers
?TSMC/Xilinx’s CoWoS
?AMD’s GPU with Hynix’s HBM and UMC’s TSV-interposer
?Nvidia’s GPU with Samsung’s HMB2 and TSMC’s TSV-interposer
Heterogeneous Integration with TSV-less Interposer
?Xilinx/SPIL’s TSV-less SLIT
?SPIL/Xilinx’s TSV-less NTI
?Amkor’s TSV-less SLIM
?ASE’s TSV-less FOCoS
?MediaTek’s TSV-less RDLs by FOWLP
?Intel’s TSV-less EMIB
?Intel/AMD’s TSV-less EMIB for CPU, GPU, and HBM
?Intel’s Knight-Landing with Micron’s HMC on TSV-less Organic Interposer
?Cisco/eSilicon’s TSV-less Organic Interposer
?ITRI’s TSV-less TSH
?Shinko’s TSV-less i-THOP

Additional information

Co-Organized by: Informatics and Control Technologies Section, IET Hong Kong
              Electronics Packaging Society, IEEE Hong Kong

Registration information

Enquiry: Dr. Law Yi Kei Owen (email: owenyklaw@yahoo.com.hk)
   


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