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Topic Title: Matrix Processing Core VHDL
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Created On: 24 December 2012 04:24 PM
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 24 December 2012 04:24 PM
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devilmusic

Posts: 13
Joined: 07 February 2010

I am doing a project called Matrix Processing Core and I had written the codes in Xilinx for it. However, the ISE could not Map,Place and Route my codes. There was no written error so I hope some one can help pin point my mistake. Below are my codes:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity MatProCore2 is
Port ( Reset, Clock, WriteEnable, BufferSel, OP : in STD_LOGIC;
WriteAddress : in STD_LOGIC_VECTOR (3 downto 0);
WriteData : in STD_LOGIC_VECTOR (7 downto 0);
ReadAddress : in STD_LOGIC_VECTOR (3 downto 0);
ReadEnable : in STD_LOGIC;
ReadData : out STD_LOGIC_VECTOR (8 downto 0);
ReadReady : out STD_LOGIC);
end MatProCore2;

architecture Behavioral of MatProCore2 is

COMPONENT dpramA -- DPRAM A
PORT (
clka : IN STD_LOGIC; --Clock
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0); --WriteEnableA
addra : IN STD_LOGIC_VECTOR(3 DOWNTO 0); --Address Port A DPRAM A
dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0); --Input DRRAM A
clkb : IN STD_LOGIC;
enb : IN STD_LOGIC; --ReadEnable A
addrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);--Address Port B DPRAM A
doutb: OUT STD_LOGIC_VECTOR(7 DOWNTO 0) -- Output DPRAM A
);
END COMPONENT;

COMPONENT dpramB16x8 --DPRAM B
PORT (
clka : IN STD_LOGIC; --Clock
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0); --WriteEnableB
addra : IN STD_LOGIC_VECTOR(3 DOWNTO 0); --Address Port A DPRAM B
dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0); --Input DPRAM B
clkb : IN STD_LOGIC;
enb : IN STD_LOGIC; --ReadEnable B
addrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);--Address Port B DPRAM B
doutb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) --Output DPRAM B
);
END COMPONENT;

COMPONENT dpram16x9
PORT (
clka : IN STD_LOGIC; --Clock
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0); --WriteEnableC
addra : IN STD_LOGIC_VECTOR(3 DOWNTO 0);--Address Port A DPRAM C
dina : IN STD_LOGIC_VECTOR(8 DOWNTO 0); --Input DPRAM C
clkb : IN STD_LOGIC;
enb : IN STD_LOGIC; --ReadEnableC
addrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);--Address Port B DPRAM C
doutb : OUT STD_LOGIC_VECTOR(8 DOWNTO 0)--Output DPRAM C
);
END COMPONENT;

-------------------------STATESIGNALS-------------------------------------
type statetype is (Idle, WriteIN, ReadIN, WriteOUT, Complete);
signal PRESstate: statetype;
signal NEXTstate: statetype;
--------------------------------------------------------------------------
signal icounter: unsigned(3 DOWNTO 0);
signal iWriteInputEnableA, iWriteInputEnableB, iWriteOutputEnable: STD_LOGIC_VECTOR(0 DOWNTO 0);
signal iReadFromA, iReadFromB: STD_LOGIC_VECTOR(7 DOWNTO 0);
signal iResizeFromA, iResizeFromB, temp: SIGNED(8 DOWNTO 0);
signal iReadInputEnable, CounterReset, CounterON: STD_LOGIC;

begin

iResizeFromA <= resize(signed(iReadFromA),9);
iResizeFromB <= resize(signed(iReadFromB),9);

DPA : dpramA
PORT MAP (
clka => Clock,
wea => iWriteInputEnableA,
addra => WriteAddress,
dina => WriteData,
clkb => Clock,
enb => iReadInputEnable,
addrb => std_logic_vector(icounter),
doutb => iReadFromA
);

DPB : dpramB16x8
PORT MAP (
clka => Clock,
wea => iWriteInputEnableB,
addra => WriteAddress,
dina => WriteData,
clkb => Clock,
enb => iReadInputEnable,
addrb => std_logic_vector(icounter),
doutb => iReadFromB
);

DPC : dpram16x9
PORT MAP (
clka => Clock,
wea => iWriteOutputEnable,
addra => std_logic_vector(icounter),
dina => std_logic_vector(temp),
clkb => Clock,
enb => ReadEnable ,
addrb => ReadAddress,
doutb => ReadData
);

Global: process (Clock) is
begin

if RISING_EDGE(Clock) then
if Reset = '1'then
PRESstate <= Idle;
else
PRESstate <= NEXTstate;
end if;

if CounterReset = '1' then
iCounter <= (others => '0');
else
iCounter <= iCounter + 1;
end if;
end if;

end process Global;

Operations: process (PRESstate, WriteEnable, BufferSel, OP, iCounter, iResizeFromA, iResizeFromB) is
begin

---Default values-------------
NEXTstate <= PRESstate;
CounterReset <= '0';
CounterON <= '1';
iReadInputEnable <= '0';
iWriteOutputEnable(0) <= '0';
ReadReady <= '0';
iWriteInputEnableA(0) <= '0';
iWriteInputEnableB(0) <= '0';
------------------------------
if (OP = '1') then
temp <= (iResizeFromA + iResizeFromB);
else
temp <= (iResizeFromA - iResizeFromB);
end if;

if (BufferSel = '1') then
iWriteInputEnableA(0) <= '1';
else
iWriteInputEnableB(0) <= '1';
end if;

case PRESstate is
when Idle =>
if (WriteEnable = '1') then
NEXTstate <= WriteIn;
else
CounterReset <= '1';
end if;

when WriteIn =>
if (icounter = "1111") then
CounterReset <= '1';
NEXTstate <= ReadIn;
end if;

when ReadIN =>
iReadInputEnable <= '1';
CounterON <= '0';
NEXTstate <= WriteOut;

when WriteOUT =>
iWriteOutputEnable(0) <= '1';
if (icounter = "1111") then
CounterReset <= '1';
NEXTstate <= Complete;
else
NEXTstate <= ReadIN;
end if;

when Complete =>
ReadReady <= '1';
NEXTstate <= Idle;

end case;

end process Operations;
end Behavioral;
Statistics

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